Skip to content

fix: preserve LLVM vector value dominance across control flow - #20111

Open
mvanhorn wants to merge 1 commit into
apache:mainfrom
mvanhorn:fix/20015-llvm-vector-dominance
Open

fix: preserve LLVM vector value dominance across control flow#20111
mvanhorn wants to merge 1 commit into
apache:mainfrom
mvanhorn:fix/20015-llvm-vector-dominance

Conversation

@mvanhorn

Copy link
Copy Markdown
Contributor

LLVM code generation rejects valid vectorized TIR produced by Relax avg_pool2d for shapes such as [1, 4, 6, 3], reporting that one shufflevector instruction does not dominate a later use. The reporter supplied a second silu reproducer with a different shape, showing that the defect is in the shared TIR-to-LLVM path rather than pooling legalization. Both failures involve vector values assembled around conditional control flow, while the Relax IR and generated TIR remain valid. The issue is open and unassigned, but two earlier cross-referenced pull requests (#20024 and #20025) closed without landing.

Testing

  • Compile the reduced vectorized TIR reproducer for LLVM and confirm module verification succeeds instead of reporting a non-dominating shufflevector.
  • Exercise the same control-flow/vector assembly pattern with the uneven lane grouping exposed by the avg_pool2d case and verify the generated function executes with the expected numeric output.
  • Exercise the alternate vector shape derived from the reporter's silu variant so the regression is not coupled to pooling legalization or a single tensor layout.
  • Retain a lazy conditional case whose unselected branch contains a potentially unsafe load, proving the dominance fix does not replace tirx.if_then_else with eager evaluation.

What changed

Reduce the two Relax examples to the smallest vectorized TIR expression that reproduces the invalid SSA graph, then add it to the LLVM codegen suite so the regression is owned at the failing backend boundary. Adjust CodeGenLLVM's lowering of branch-bearing vector expressions so every value consumed after a control-flow merge is produced in a dominating block (or represented by the merge value), and branch-local shuffle/concat values cannot escape into a sibling or successor path. Preserve lazy tirx.if_then_else behavior for unsafe operands and the existing vector concatenation semantics; do not special-case avg_pool2d, silu, or the reported dimensions.

Fixes #20015

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

[Bug] LLVM CodeGen Crash on avg_pool2d with Specific Shape

1 participant