feat(npu): Ascend platform, MindIE attention, and Ulysses SP for v1 - #270
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feat(npu): Ascend platform, MindIE attention, and Ulysses SP for v1#270Chitandaaaaa wants to merge 5 commits into
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Add platforms registry with Ascend capability probes, extend utils/platform for npu/hccl/compile kwargs, and register a MindIE attention backend for Qwen-Image on the v1 layout. Co-authored-by: Cursor <cursoragent@cursor.com>
Bind Ascend devices before HCCL init_process_group, align/bind config.device across engine workers, and reject MindIE with ring SP. Co-authored-by: Cursor <cursoragent@cursor.com>
Use addcmul for gated residual/modulate micro-opts, and gate MindIE RoPE / layernorm_scale_shift behind USE_MINDIESD_FUSE. Co-authored-by: Cursor <cursoragent@cursor.com>
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under Ulysses SP, hiding all-to-all latency behind FA compute (compute-communication overlap). - Ulysses flow via all_to_all_4D_pre/single/after (SeqAllToAll4D). - FA_ALLTOALL_CUT/OVERLAP count semantics (0/1 off, >1 on, CUT wins): baseline single round trip; cut = head-chunked round trips; overlap = all-to-all on side stream2 overlapped with FA on main stream via npu Event/Stream sync. - current_stream refreshed at forward time. - Ulysses-only; falls back to USPAttention when not available.
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Summary
Port Ascend NPU support onto the
v1architecture (capability-level migration from fork PR #11 onmain; not a cherry-pick).platforms/(Ascend capability probes, HCCL, MindIE compile backend), extendutils/platform.pyfor NPU/HCCL/get_compile_kwargs(), and register amindieattention backend for Qwen-Image.init_process_group(HCCL), align/bindconfig.devicein engine/worker, and reject MindIE attention withring > 1.addcmulfor gated residual/modulate; gate MindIE RoPE /layernorm_scale_shiftbehindUSE_MINDIESD_FUSE=1.Commits
bf49ef1feat(npu): add Ascend platform abstraction and MindIE attention8c1e61cfeat(npu): enable Ulysses SP with CFG parallel on Ascend0cf05b6feat(npu): fuse Qwen DiT addcmul, MindIE RoPE, and LN modulateNotes
use_torch_compile=False); compile kwargs are injected only when compile is on.USE_MINDIESD_FUSEonly gates MindIE RoPE / LN fuse;addcmulis always on (generic torch op).device/device_typeis explicit.Test plan
--attn-type mindie(and without).ASCEND_RT_VISIBLE_DEVICES=0,1,2,3, Ulysses SP (sp_ulysses_degree=4,sp_ring_degree=1) + CFG parallel.USE_MINDIESD_FUSE=1for RoPE / LN fuse path.ring > 1is rejected with a clear error.